Field of the Invention
The invention relates to a digital current switch having the following characteristics:
(a) at least one first and one second transistor being coupled at a first terminal of each main current path and connected through a controllable current source to a terminal for a first supply potential; PA1 (b) a control input of the first transistor being a terminal for an input signal, and a control input of the second transistor being a terminal for a reference signal; PA1 (c) second terminals of the main current paths of the transistors being connected to a terminal for a second supply potential; and PA1 (d) the second terminal of the main current path of at least one of the transistors being connected to an output signal terminal and through a resistor to the terminal for the second supply potential.
Such circuits are known, for instance, from Published European Application No. 0 436 823 A1. If bipolar transistors are used as switching transistors, that circuitry technique is known as CML or current mode logic if the output is connected directly to the operating resistor, and as ECL or emitter-coupled logic if the output is connected to the operating resistor through an emitter follower. The output of the switching stage is generally loaded by a capacitor. The capacitor is essentially composed of the parasitic capacitances of the switching transistors, the input transistors of following switching stages, and a connecting line. During a switching process, the capacitor is charged in the opposite direction. The charge current flows either through the operating resistor or emitter follower transistor, or through the current source of the current switch or the current source of the emitter follower. Those circuits are typically produced in the form of integrated circuits. The absolute specifications of the components have a relatively wide range of fluctuation. Moreover, the transistor parameters, such as current amplification and base-to-emitter voltage, are relatively strongly temperature-dependent. Therefore, the currents delivered or picked up at the output of the switching stage, for reversing the charge of the parasitic capacitors, are process and temperature-dependent. Heretofore, in order to achieve the necessary speed requirements, the circuits have been dimensioned in accordance with the most unfavorable possible conditions. That means that in order to achieve a predetermined level rise at the operating resistor, the resistance is low, while in return the current impressed by the current source of the current switch or of the emitter follower transistor is dimensioned to be high. That has the disadvantage of relatively high power loss under normal operating conditions.